1. Field of the Invention
The present invention relates to a pseudostatic random access memory (pseudo-SRAM) in which refresh is performed in a self-refresh mode of a waiting state.
2. Description of the Prior Art
Since a memory cell structure of a dynamic random access memory (DRAM) is simple, a DRAM having a large memory capacity can be inexpensively produced. However, such a DRAM has a disadvantage in that the refresh operations are complicated. In order to cope with the disadvantage, a pseudo-SRAM has been developed. The pseudo-SRAM has a memory cell structure as simple as a DRAM, and the refresh operations can easily be conducted. Therefore, the pseudo-SRAM can be used as if it were a static random access memory (SRAM). In such a pseudo-SRAM, as in the general DRAM, two bit lines of a bit-line pair are first precharged to a potential level of HV.sub.CC which is half of a supply voltage of V.sub.CC by a precharge circuit. Then, data is read from a memory cell or refresh is performed.
FIG. 3 shows a precharge circuit used in such a prior art pseudo-SRAM. In the precharge circuit, two bit lines 11a and 11b of each bit-line pair 11 are shorted by setting a control signal A active during the precharge period. At the same time, a control signal B is made active, so that the respective bit lines 11a and 11b are connected to an HV.sub.CC generating circuit 13 via a common line 12. The HV.sub.CC generating circuit 13 generates a potential level of HV.sub.CC which is half of a supply voltage of V.sub.CC by potential dividing resistors R.sub.11 and R.sub.12 which have the same resistance values. The generated potential level of HV.sub.CC is output to the common line 12 via a current mirror circuit. Therefore, the potential levels of the bit lines 11a and 11b are fixed at the potential level of HV.sub.CC by the precharge circuit as a result of precharge.
In such a prior art pseudo-SRAM, it is necessary to perform the refresh operation in an adjusted manner with respect to the reading and writing operation in a normal mode. In the self-refresh mode, the refresh operation can be performed in an asynchronous manner with the external. In the self-refresh mode, each interval between refresh actions corresponds to a precharge period.
If the time period of the refresh cycle can be made longer in the self-refresh mode, the power consumption of the pseudo-SRAM can be reduced, so that the data can be retained for a long time even when a battery is used as the power supply.
However, in a case where the time period of the refresh cycle is merely made longer, a High level potential stored in a memory cell is dropped down to the vicinity of the potential level of HV.sub.CC due to a leak current, so that it becomes impossible to obtain a sufficient margin between the lowered potential level stored in the memory cell and the potential level of HV.sub.CC. This results in an error operation of the refresh. If the potential level of the bit lines 11a and 11b is forcedly dropped below the potential level of HV.sub.CC in order to obtain a sufficient margin, a large current is required to drop the potential level of the bit lines 11a and 11b. This causes an increase in power consumption.
As apparent from the above, the prior art pseudo-SRAM has a problem that, even if the time period of the refresh cycle in the waiting state is made longer, the power consumption cannot be reduced.